eVS has internally developed a non-stop evolution product line related to 2D/3D image processing algorithm in FPGA suitable for embedded systems like smart cameras or video processors, where strong integration, high computation capability, low power consumption, flexibility and reconfigurability are particularly required features.
| IP² core lib (Image Processing IP core library) is a library of basic vision algorithms for real-time image processing and video data manipulation in FPGA. It was designed to provide most of the algorithms required when an application is asked to rely on vision to make decisions and control. [Continue...] | |
| SVC (Stereo Vision Core) is a stereo vision engine for real-time three-dimensional data extraction. It exploits a technology based on an advanced correlation algorithm in FPGA to recover the three-dimensional structure of the scene observed by a couple of cameras. SVC is provided as FPGA IP core. [Continue...] | |
![]() | Implifico is a post processing software for image magnification in video surveillance. If in a video sequence the object of interest is seen in a number of frames, Implifico is able to create a high-resolution image of this object. [Continue...] | |

