IP² core lib is available as functional block set for Xilinx System Generator for DSP. It extends the environment adding several high level functionalities specialized for image processing. Leveraging on the unique SysGen features, IP² core lib makes easy linking, configuring and building modules suitable for the target application. SysGen provides facilities to simulate the resulting design as well as generating VHDL/Verilog code, the netlist or bitstream and program the FPGA.

Exploiting the potential of System Generator, it is even possible co-simulating the design directly on target using the so called “hardware in the loop” technique. Thus, starting from a modular flexible and well tested architecture, results reducing the time to market to build an application.

KEY FEATURES

• Real time performance
• Self-contained modules
• Compact configuration
• Common interface
• High modularity for different contexts
• Optical (2D) and range (3D) image support

• bitstream for a specific hardware platform to be integrated with the end user FPGA design
• netlist to provide a portable solution towards different platforms
• RTL VHDL source code to supply the FPGA designers with ultimate flexibility
• Simulink Block Set to extend Xilinx System Generator for DSP