eVS - embedded Vision Systems - prodotti

 

SVC (Stereo Vision Core) is a stereo vision engine for real-time tridimensional data extraction. It exploits a technology based on an advanced correlation algorithm in FPGA to recover the tridimensional structure of the scene observed by a couple of cameras. SVC is provided as FPGA IP core.

Computational stereopsis means processing a pair of images coming from two cameras (watching the same scene from two different points of view) to obtain depth information. Range and accuracy measures depend on both cameras resolution, baseline, and focal length. Thus, the stereo setup must be configured according to your specific application needs. Depth maps are typically obtained using correlation. Getting a dense and accurate depth map is a very high computational cost task. SVC makes the process directly in hardware, parallelizing the computation and reaching a frame rate greater than 150 fps at 256x256 pixels resolution.

SVC is designed for applications requiring robustness and high performance in terms of both quality and speed. Typical scenarios for industrial automation are grasping and positioning of pieces through robot arms, or autonomous guided vehicle (AGV) navigation. Other possible application scenarios are in automotive, domotics, building automation, security, and surveillance.

SVC can be used either on stand-alone embedded platforms, programmable data acquisition board, and vision processors. Both FPGA resource occupation and performances are scalable to fit custom requirements and the reference hardware architecture. SVC is a self-contained module fully compliant with eVS IP² core lib.

KEY FEATURES

  • Real-time 3D data extraction
  • Self-contained module
  • Compact configuration
  • Robust to brightness changes
  • Sub pixel accuracy

AVAILABLE SOLUTIONS

  • bitstream for a specific hardware platform to be integrated with the end user FPGA design
  • netlist to provide a portable solution towards different platforms
  • RTL VHDL source code to supply the FPGA designers with ultimate flexibility
  • Simulink Block Set to extend Xilinx System Generator for DSP
Stereo camera
Stereo 0 Stereo 1

For a deeper analysis consult the technical characteristics page: